The inventive concepts described herein relate to memory devices, and more particularly to an impedance calibration circuit of a semiconductor memory device, a semiconductor memory device and a method of operating a semiconductor memory device.
As the operating speed of semiconductor memory devices has increased, swing width of signals interfaced between a semiconductor memory device and a memory controller has generally decreased. However, as swing width has decreased, signals transferred between a semiconductor memory device and a memory controller may be more easily distorted by impedance mismatch caused by process, voltage and temperature (PVT) variations. An impedance calibration operation for adjusting an output impedance and/or a termination impedance of a semiconductor memory device may be employed at transmitting and/or receiving stages of the semiconductor memory device. During the impedance calibration operation, the output impedance and/or the termination impedance may be adjusted by comparing the output impedance and/or the termination impedance with an impedance of an external resistor. The impedance calibration operation may be referred to as an input/output (I/O) offset cancellation operation or a ZQ calibration operation.